The present invention relates in general to parallel processing systems and in particular to a method and apparatusfor providing communication between concurrently operating data processing devices.
The processing time for computer operations can often be improved through the use of parallel processors. For instance when computation involves the manipulation of arrays, a special array processor can be provided for rapidly performing this function while a multipurpose processor is utilized to perform other portions of the computation. The two processors are typically interconnected through a bus system permitting the transfer of data between a memory device associated with the multipurpose processor and a memory device associated with the array processor. In some calculations further improvements in processing speed are possible by permitting more than two processors to operate concurrently on separable portions of the problem. For example, if a computation involves multiplying a three dimensional array by a two dimensional array, a separate array processor can be provided to concurrently perform the multiplication for each dimension of the array, thereby permitting multiplication of the three dimensional array in the time required to multiply only a single dimension.
The improvements in computation speed afforded through the use of parallel processing devices have been limited by the bus systems used to transfer data between processors. In the past, concurrent processors have typically been interconnected by a linear parallel bus wherein memory devices associated with each processor have been connected to separate nodes of the bus. When data from any one processor memory is placed on the bus, the data is transmitted simultaneously to every other node. Every node is assigned a unique address and a sending node suitably adds a node address to the data being sent. Each receiving node then includes means for recognizing its own address and passes the data on to its associated processing device on recognition of that address. The speed of such a linear parallel bus system is limited because only one processor can transmit data on the bus at any given time. This system does allow every processor to receive data on the bus in the instance when the interfacing equipment at each node is capable cf recognizing a universal "broadcast" address, but such a broadcast mode of operation has limited usefulness inasmuch as computations do not always require identical data to be sent to every processor in the system.
Ring buses provide some improvement over parallel buses by allowing more than one processor to transmit data at any one time. In a ring bus system, the bus nodes are arranged in a loop wherein each node is connected to its two nearest neighbors through separate, one-way buses. Data on the ring bus passes from node to node in synchronous fashion according to a system clock signal, with each node passing incoming data either to a processor associated with that node, or on to the next node on the loop. A node can also receive data from its a$sociated processor and transmit it to the nearest neighbor node.
Each node in a ring bus system is assigned a unique address, with the data carried on the bus including the address of the node which is to receive the data. If a given node receives data addressed to another node, it passes the data to the next node on the next system clock cycle, but if a node receives data addressed to that node, the data is transmitted to the associated processor. The node may place new data from its associated processor on the bus by transmitting it to its nearest neighbor. Thus more than one processor may place data on the ring bus at any given time whereby the ring bus generally permits more efficient use of the bus bandwidth than a linear parallel bus system. However, since each node can only receive or pass on data, but not both, only one processor can receive any given data transmission on the bus.
What is needed and would be desirable is a bus system permitting simultaneous data transfer between a plurality of concurrently operating data processing devices, allowing many processors to transmit data simultaneously, while permitting any processor to transmit the same data to any other processor or selected group of processors.